1. Field of the Invention
The present invention relates to a method for driving a thin film transistor-liquid crystal display (hereinafter referred to as a TFT-LCD), and more particularly, to a method for driving a TFT-LCD panel using a line inversion driving method.
2. Discussion of the Related Art
A TFT-LCD panel has a pixel array made of a plurality of pixels. FIGS. 1A and 1B show an equivalent circuit diagram for each pixel. Each pixel of the pixel array is connected to a cross point between a scanning line and a data line which meet at a right angle. FIG. 1A is an equivalent circuit diagram of pixels using a storage-on-gate type arrangement in which an auxiliary capacitor C.sub.s for voltage maintenance is formed on the next gate or the previous gate, irrespective of a common electrode. FIG. 1B is an equivalent circuit diagram in which a pixel electrode C.sub.LC and an auxiliary capacitor C.sub.s are connected to a common electrode.
As shown in FIG. 1A, a gate line (e.g., a scanning line or a word line) connected to a gate of a thin film transistor (TFT) applies a driving voltage V.sub.gn to the gate of the TFT. A video data signal V.sub.sig is applied to the drain of the TFT. One terminal of the pixel electrode C.sub.LC is connected to a source of the TFT. The other terminal of the pixel electrode C.sub.LC is connected to a common voltage V.sub.com. One terminal of the auxiliary capacitor C.sub.s for maintaining voltage is connected to the pixel electrode C.sub.LC in parallel. Finally, the other terminal of the auxiliary capacitor C.sub.s applies the next scanning line voltage V.sub.gn-1.
As shown in FIG. 1B, a scanning line driving voltage V.sub.gn is applied to the gate of a TFT. A video data signal V.sub.sig is applied to the drain of the TFT. One terminal of the pixel electrode C.sub.LC and the auxiliary capacitor C.sub.s are connected to a source of the TFT. The other terminals of the pixel electrode C.sub.LC and the auxiliary capacitor C.sub.s are connected to a common voltage V.sub.com.
When driving such pixel arrays, if a voltage is applied to a liquid crystal pixel in only one way, degradation of the liquid crystal is accelerated. To avoid this degradation, a video data voltage applied to the liquid crystal periodically oscillates between two levels having opposite polarities. In this case, the polarity of the data voltage should be inverted every field. There are preferably two methods: a field inversion driving method for inverting the polarity of a driving voltage of all pixels of the panel in every field, and a line inversion driving method for alternately inverting the polarity of the driving voltage of every pixel line connected to one scanning line. When inverting the voltage polarity according to the above two methods, a pixel voltage applied to a pixel electrode connected to a drain of the TFT should be positive or negative with respect to the common voltage V.sub.com.
To apply the data voltage to a pixel of the panel, the TFT should be turned on by applying a driving voltage to a gate of the TFT. FIGS. 2 and 3 show a method for driving a gate voltage at a gate of the TFT, for driving a data voltage at a drain of the TFT, and for driving a common voltage applied to a node of V.sub.com. FIG. 2 shows a driving method using gate voltage having two levels. FIG. 3 shows a floating gate driving method for floating a gate driving voltage used in a cell array of a storage-on-gate type arrangement in order to maintain a constant phase difference between the gate driving voltage and the common voltage.
In the method for driving a TFT-LCD panel using a line inversion driving method, a polarity of V.sub.sig should be opposite that of V.sub.com every line. In a single pixel, such polarity characteristics are presented such that polarities of V.sub.sig and V.sub.com are alternately inverted with respect to each other.
FIG. 2 shows a gate pulse driving method in which a low level of a gate voltage maintains a constant voltage level. Since a pixel voltage V.sub.p is higher than V.sub.com in timing pulse period (a), and the pixel voltage V.sub.p is lower than V.sub.com in timing pulse period (d), there is a difference between a gate to source voltage V.sub.gs and a drain to source voltage V.sub.ds in each time period. That is, there is a positive field and a negative field. Herein, the positive field shows that the pixel electrode is charged as a positive voltage higher than V.sub.com as shown in timing pulse period (a). Further, the negative field shows that the pixel electrode is charged as a negative voltage lower than V.sub.com as shown in timing pulse period (d).
Likewise, FIG. 3 shows a gate pulse driving method in which a low level of the gate voltage is floated. Since a pixel voltage V.sub.p is higher than V.sub.com in timing pulse period (a), and the pixel voltage V.sub.p is lower than V.sub.com in timing pulse period (d), there is a difference between drain to source voltages V.sub.ds in each time period, thereby causing a positive field and a negative field.
FIGS. 4A and 4B show an example of a voltage of each node of a TFT for each timing pulse period using a gate according to FIG. 2. Reference characters (a)-(f) in FIGS. 4A-5B represent the time periods in FIGS. 2 and 3. Accordingly, V.sub.p "0.5V(c)" represents a pixel voltage in timing pulse period (c).
FIG. 2 is an example showing that a voltage difference between a gate to source voltage and a source to drain voltage occurs. As shown in FIG. 2, a difference between V.sub.gs of a positive field and V.sub.gs of a negative field increases over the period between timing pulse periods (b) and (c), when the scanning line connected to the pixels is sequentially selected.
To display an entire screen as a color of a constant brightness and to achieve the same color and brightness of every pixel while displaying the entire screen, three signals are employed. That is, a gate driving pulse is shown as a rectangular wave signal ranging from -15V to +10V, data signal V.sub.sig is shown as a second rectangular wave signal ranging from -2.8V to +1.2V, and a common voltage V.sub.com is shown as a third rectangular wave signal ranging form -3.8V to +1.2V.
As shown in FIG. 4A, when a positive field is applied to the pixel and a gate driving pulse of -15V is in timing pulse period (a), the TFT is turned on by applying a voltage of +10V. When a data voltage of +0.8V is applied to a drain, a voltage drop of 0.3V occurs and then +0.5V is applied to the pixel electrode. Therefore, -3.8V is applied to V.sub.com, and a voltage difference 4.3V is charged to the pixel electrode which is a capacitor between a pixel electrode and a common electrode.
In a timing pulse period (b) in which a second scanning line is selected, a gate driving pulse is -15V, a data signal V.sub.sig is -2.8V, and a common voltage V.sub.com is +1.2V. V.sub.p of a pixel electrode is higher than V.sub.com by +4.3V, that is, V.sub.p is expressed as 4.3V +1.2V=5.5V, thus V.sub.p becomes a high state.
In a timing pulse period (c) in which a third scanning line is selected, the gate driving pulse is -15V, the data signal V.sub.sig is +0.8V, and the common voltage V.sub.com is -3.8V. Thus, V.sub.p of the pixel electrode becomes a low state of +0.5V, since V.sub.com is -3.8V.
As shown in FIG. 4B, when a negative field is applied to pixel and an initial gate potential is -15V is in a timing pulse period (d), the TFT is turned on by applying a voltage of +10V to the gate. When a data voltage of -2.8V is applied to a drain, a voltage drop of 0.3V occurs and then -3.1V is applied to the pixel electrode. Therefore, +1.2V is applied to V.sub.com, a voltage difference 4.3V is charged to the pixel electrode like the preceding positive field. However, the pixel electrode is charged by a more negative field than the node of V.sub.com.
In timing pulse period (e) in which the next scanning line is selected. The gate driving pulse is -15V, the data signal V.sub.sig is +0.8V, and the common voltage V.sub.com is -3.8V. Thus, V.sub.p of the pixel electrode is expressed as (-3.8V)+(-4.3V)=-8.1V, thus V.sub.p becomes a low state.
In timing pulse period (f) in which the next scanning line is selected, the gate driving pulse is -15V, the data signal V.sub.sig is -2.8V, and the common voltage V.sub.com is +1.2V. Thus, V.sub.p of the pixel electrode becomes a high state of -3.1V.
Under these operations, in the case of timing pulse period (b) of the positive field shown in FIG. 4A, each voltage between terminals of TFT is as follows. A gate to source voltage V.sub.gs is expressed as [-15 -5.5]=-20.5V, a drain to source voltage V.sub.ds is expressed as [-2.8-5.5]=-8.3V, and a gate to drain voltage V.sub.gd is expressed as [-15-(-2.8)]=-12.2V.
In the timing pulse period (c), the gate to source voltage V.sub.gs is expressed as [-15-0.5]=-15.5V, the drain to source voltage V.sub.ds is expressed as [-0.8+0.5]=-0.3V, and the gate to drain voltage V.sub.gd is expressed as [-15-0.8]=-15.8V.
Next, in the case of timing pulse period (e) of the negative field shown in FIG. 4B, each of the voltage between terminals of TFT is as follows. A gate to source voltage V.sub.gs is expressed as [-15-(-8.1)]=-6.9V, a drain to source voltage V.sub.ds is expressed as [0.8-(-8.1)]=8.9V, and a gate to drain voltage V.sub.gd is expressed as [-15-0.8]=-15.8V.
In timing pulse period (f), the gate to source voltage V.sub.gs is expressed as [-15-(-3.1)]=-11.9V, the drain to source voltage V.sub.ds is expressed as [-2.8-(-3.1)]=0.3V, and the gate to drain voltage V.sub.gd is expressed [-15-(-2.8)]=-12.2V.
As described above, there is a voltage difference between the nodes of the TFT while scanning both the positive field and the negative field. For example, a V.sub.gs of -20.5V in the time pulse period (b) of the positive field is changed to a V.sub.gs of -6.9V in time pulse period (e) of the negative field, V.sub.ds ranges from -8.3V to -8.9V, and V.sub.gd ranges from -12.2V to -15.8V.
In addition, a V.sub.gs of -15.5V in time pulse period (c) of the positive field is changed to a V.sub.gs of -11.9V in time pulse period (f) of the negative field, V.sub.ds ranges from -0.3V to -0.3V, and V.sub.gd ranges from -15.8V to -12.2V. As a result, these voltage variations cause unstable leakage current in the TFT, and the unstable leakage current is periodically generated when scanning in the positive field and the negative field, thereby causing a 30 Hz flicker.
FIGS. 5A and 5B show each node voltage of a TFT using the floating gate driving method shown in FIG. 3, in which even though a voltage difference of V.sub.gs between the positive field and negative field is decreased, a voltage difference of V.sub.ds is still high.
In the floating gate driving method, in the case of timing pulse period (b) for selecting the next scanning line, a gate driving pulse is -10V as a high level, data signal V.sub.sig is -2.8V as a low level, and a common voltage V.sub.com is 1.2V as a high level.
In timing pulse period (c) for selecting the next scanning line, the gate driving pulse is -15V as a low level, and the data signal V.sub.sig is +0.8V as a high level, the common voltage V.sub.com is -3.8V as a low level.
As shown in FIG. 5A, when a positive field is applied to pixel in timing pulse period (b), the gate driving pulse is -10V as a low level, the data signal V.sub.sig is -2.8V as a low level, and the common voltage V.sub.com is +1.2V as a high level. Thus, V.sub.p of the pixel electrode becomes a high state of 5.5V.
In timing pulse period (c), the gate driving pulse is -15V as a low level, the data signal V.sub.sig is +0.8V as a high level, and the common voltage V.sub.com is -3.8V as a low level. Thus, V.sub.p of the pixel becomes a low state of +0.5V.
As shown in FIG. 5B, when a negative field is applied to a pixel in a timing pulse period (e), the gate driving pulse is -15V as a low level, the data signal V.sub.sig is +0.8V as a high level, and the common voltage V.sub.com is -3.8V as a low level. Thus, V.sub.p of the pixel becomes a low state of -8.1V.
In timing pulse period (f), the gate driving pulse is -10V as a high level, the data signal V.sub.sig is -2.8V as a low level, and the common voltage V.sub.com is +1.2V as a high level. Thus, V.sub.p of the pixel becomes a high state of -3.1V.
In the case of timing pulse period (b) of the positive field shown in FIG. 5A, each voltage between terminals of the TFT is as follows. A gate to source voltage V.sub.gs is expressed as [-10-5.5]=-15.5V, a drain to source voltage V.sub.ds is expressed as [-2.8-5.5]=-8.3V, and a gate to drain voltage V.sub.gd is expressed as [-10-(-2.8)]=-8.2V.
In the timing pulse period (c) shown in FIG. 5A, the gate to source voltage V.sub.gs is expressed as [-15-0.5]=-15.5V, the drain to source voltage V.sub.ds is expressed as [0.8-0.5]=0.3V, and the gate to drain voltage V.sub.gd is expressed as [-15-0.8]=-15.8V.
In the case of timing pulse period (e) of the positive field shown in FIG. 5B, each voltage between the terminals of the TFT is as follows. A gate to source voltage V.sub.gs is expressed as [-15-(-8.1)]=-6.9V, a drain to source voltage V.sub.ds is expressed as [0.8-(-8.1)]=8.9V, and a gate to drain voltage V.sub.gd is expressed as [-15-0.8]=-15.8V.
In timing pulse period (f) shown in FIG. 5B, the gate to source voltage V.sub.gs is expressed as [-10-(-3.1)]=-6.9V, the drain to source voltage V.sub.ds is expressed as [-2.8-(-3.1)]=0.3V, and the gate to drain voltage V.sub.gd is expressed as [-10-(-2.8)]=-7.2V.
There is no variation of V.sub.gs in the floating gate driving method. However, there is a voltage variation in V.sub.ds and V.sub.gd because V.sub.ds is expressed as V.sub.ds(b) -V.sub.ds(e) =-8.3-8.9 =-17.2 and V.sub.gd is expressed as V.sub.gd(b) -V.sub.gd(e) =-8.2-(-15.8)=7.6V.
As described above, such voltage variations between the terminals of a TFT causes the screen to flicker. The flicker can be explained by FIG. 6 which shows the characteristics of current versus voltage in the TFT.
As shown in FIGS. 6 and 7, leakage current occurs in an OFF-region according to a graph of source-to-drain current I.sub.ds. As the absolute value of V.sub.gs increases, the leakage current increases. Therefore, there is a difference of gate-to-source voltages V.sub.gs between time periods of the positive field and the negative field. Because a difference of leakage current occurs, a light transmittance is varied by a root-mean-square (rms) voltage difference between the positive field and the negative field, thereby causing a 30 Hz flicker.
FIG. 7 depicts the above operations. Although a liquid crystal voltage (position A; reference number 71) which is fully charged in the positive field is identical with another liquid crystal voltage (position B; reference number 73) which is also fully charged in a negative field, there is a voltage difference after one field, since an electric charge included in the pixel electrode is greatly discharged or minutely discharged. Accordingly, a voltage difference between a position C (72) and a position D (74) of FIG. 7 is greatly generated, thereby generating a difference between rms voltages of two fields and causing flicker.